Publications
N. M. Shehzad, A.-M. Déplanche, Y. Trinquet, R. Urunela,
Overhead control in real-time global scheduling,
In proc. of the 19th International Conference on Real-Time and Network Systems, 2011
Résumé : A number of optimal algorithms are known for scheduling of periodic tasksets with implicit deadlines on real-time multiprocessor systems. These algorithms belong to the branch of global scheduling which allows the migration of tasks between the processors. Though these are theoretically optimal, questions are raised about their practical implementation because optimality is achieved at cost of excessive scheduling points, migrations and preemptions. Controlling the overhead to a possible minimum level is one of the critical areas of research. This paper is specifically concerned with particular global scheduling algorithms that combine fluid scheduling and deadline partitioning, while guaranteeing optimality. It proposes the utilization of some heuristics to improve their performance by reducing the number of migrations and preemptions. Our simulation results validate our approach and show a significantly reduced number of migrations and preemptions when compared to a previous basic version of such a scheduling algorithm.
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N. Shezad, A-M. Déplanche, Y. Trinquet, R. Urunela,
Efficiency evaluation of overhead control heuristics in DP-Fair multiprocessor scheduling,
ETFA 2012. 17th IEEE International Conference on Emerging Technologies & Factory Automation, Krakow, Poland 17-21, Sept. 2012.
Résumé : A number of optimal algorithms exist for scheduling of periodic taskset with implicit deadlines in real-time multiprocessor systems. However, the practical facts reveal that the optimality is achieved at the cost of excessive scheduling points, migrations and preemptions. In previous work, we proposed two heuristics to control the overhead for a class of non-work conserving global scheduling algorithms that combine fluid scheduling and deadline partitioning, while guaranteeing optimality. This paper gives some detailed simulation results along with description of
the system to generate the data for the simulation. The given results show the basic strength of the heuristics and validate their efficiency.
R. Kassem, M. Briday, J.-L. Béchennec, G. Savaton et Y. Trinquet,
Résumé : Validation and Verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to the simulation of the actual binary code using an accurate model of the processor. However, for real-time applications, the simulated execution time must be as close as possible to the execution time on the actual platform and in this case the latter gives the closest results. The main drawback of the simulation of application's software using an accurate model of the processor resides in the development of a handwritten simulator which is a difficult and tedious task. This paper presents Harmless, a hardware Architecture Description Language (ADL) that mainly targets real-time embedded systems. Harmless is dedicated to the generation of simulator of the hardware platform to develop and test real-time embedded applications. Compared to existing ADLs, Harmless1) offers a more flexible description of the Instruction Set Architecture (ISA) 2) allows to describe the microarchitecture independently of the ISA to ease its reuse and 3) compares favorably to simulators generated by the existing ADLs toolsets.